1. Field of the Invention
The present invention relates to a wireless communication system. More particularly, the present invention relates to an apparatus and a method for improving performance of a half-chip interval chip equalizer in a wireless communication system.
2. Description of the Related Art
Generally, a reception end of a digital communication system estimates a channel based on a pilot signal sent by a transmitter, and trains a half-chip interval chip equalizer using the estimated channel to perform channel equalization. A channel estimator has a number of taps of a fixed length for ease of hardware design and can variably control the length of a channel estimation vector within a maximum fixed length depending on a channel environment. The channel estimator inside the equalizer may control the length of the channel estimation vector, but hardware having the number of taps of a sufficiently long fixed length should be provided with consideration of a maximum delay value even in the case where an actual channel has a sparse channel characteristic.
The conventional channel estimator of a fixed length has several problems and limitations. The conventional channel estimator has a tap of a predetermined length with consideration of a maximum delay time that may occur in a channel and an investable hardware resource. For example, a chip level equalizer provided to a reception end inside a terminal of a 3rd Generation Partnership Project (3GPP) Wideband Code Division Multiple Access (WCDMA) communication system has a 40 tap-channel estimator. Where hardware of a number of fixed taps is employed, a channel estimator operates all taps to perform channel estimation regardless of a delay time of a channel, or may perform channel estimation using only a smaller number of taps than a supportable maximum number of taps with consideration of a channel delay time.
For exceptional channel environments, for example, environments such as a riverside reflective wave, a long delay channel due to a relay, etc., a maximum delay time of a channel may be longer than a time supported by a maximum number of taps of a channel estimator inside a chip level equalizer. In this case, due to an interference effect given by a path outside a window of the equalizer, the performance of the chip level equalizer deteriorates. Furthermore, since the exceptional channel environments generally have a sparse characteristic, estimation of a meaningless noise tap is performed, so that the performance of the equalizer deteriorates and power and a hardware resource are wasted.